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rev 0.6 / mar. 2005 1 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash document title 1gbit (128mx8bit / 64mx16 bit) nand flash memory revision history revision no. history draft date remark 0.0 1) initial draft. aug. 2004 preliminary 0.1 1) correct fig.10 sequential out cycle after read 2) add the text to fig.1, table.1, table.2 - text : io15 - io8 (x16 only) 3) delete ?3.2 page program note 1. - note : if possible it is better to remove this constrain 4) change the text ( page 10,13, 45) - 2.2 address input : 28 addresses -> 27 addresses - 3.7 reset : fig.29 -> fig.30 - 5.1 automatic page read after power up : fig.30 -> fig.29 5) add 5.3 addressing for program operation & fig.34 sep. 2004 preliminary 0.2 1) change tsop, wsop, fbga package dimension & figures. - change tsop, wsop, fbga package mechanical data - change fbga thickness (1.2 -> 1.0 mm) 2) correct tsop, wsop pin configurations. - 38th nc pin has been changed lockpre (figure 3,4) 3) edit figure 15,19 & table 4 4) add bad block management 5) change device identifier 3rd byte - 3rd byte id is changed. (reserved -> don't care) - 3rd byte id table is deleted. oct. 2004 preliminary 0.3 1) add errata 2) lockpre is changed to pre. - texts, table, figures are changed. 3) add note.4 (table.14) 4) block lock mechanism is deleted. - texts, table, figures are deleted. 5) add application note(power-on/off sequence & auto sleep mode.) - texts & figures are added. 6) edit the figures. (#10~25) nov.29 2004 preliminary 0.4 1) change ac characteristics(treh) before: 20ns -> after: 30ns 2) edit note.1 (page. 21) 3) edit the application note 1,2 4) edit the address cycle map (x8, x16) jan.19 2005 preliminary tcls tclh twp tals talh tds twc tr specification 0 10 25 0 10 20 50 25 relaxed value 5 15 40 5 15 25 60 27 ( datasheet : )
rev 0.6 / mar. 2005 2 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash revision history - continued - revision no. history draft date remark 0.5 1) correct ac characteristics(treh) before: 30ns-> after: 20ns 2) add errata jan. 25. 2005 preliminary 0.6 1) change ac characteristics 2) add tadl parameter - tadl=100ns 3) correct table.9 mar. 09. 2005 preliminary case trc trp treh trea specification read(all) 50 20 20 30 relaxed value except for id read 50 20 20 30 id read 60 25 30 30 tdh before 10 after 15
rev 0.6 / mar. 2005 3 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 or x16 bus width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : hy27ufxx1g2m - 1.8v device: vcc = 1.7 to 1.95v : hy27sfxx1g2m memory cell array = (2k+ 64) bytes x 64 pages x 1,024 blocks = (1k+32) words x 64 pages x 1,024 blocks page size - x8 device : (2k + 64 spare) bytes : hy27(u/s)f081g2m - x16 device: (1k + 32 spare) words : hy27(u/s)f161g2m block size - x8 device: (128k + 4k spare) bytes - x16 device: (64k + 2k spare) words page read / program - random access: 25us (max.) - sequential access: 50ns (min.) - page program time: 300us (typ.) copy back program mode - fast page copy without external buffering cache program mode - internal cache register to improve the program throughput fast block erase - block erase time: 2ms (typ.) status register electronic signature - manufacturer code - device code chip enable don't care option - simple interface with microcontroller automatic page 0 read at power-up option - boot from nand support - automatic memory download serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles - 10 years data retention package - hy27(u/s)f(08/16)1g2m-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27(u/s)f(08/16)1g2m-t (lead) - hy27(u/s)f(08/16)1g2m-tp (lead free) - hy27(u/s)f(08/16)1g2m-v(p) : 48-pin wsop1 (12 x 17 x 0.7 mm) - hy27(u/s)f(08/16)1g2m-v (lead) - hy27(u/s)f(08/16)1g2m-vp (lead free) - hy27(u/s)f(08/16)1g2m-f(p) : 63-ball fbga (9.5 x 12 x 1.0 mm) - hy27(u/s)f(08/16)1g2m-f (lead) - hy27(u/s)f(08/16)1g2m-fp (lead free)
rev 0.6 / mar. 2005 4 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 1. summary description the hynix hy27(u/s)f(08/16)1g2m series is a 128mx8bit with spare 4mx8 bit capacity. the device is offered in 1.8v vcc power supply and in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased indepe ndently so it is possible to preserve valid data while old data is erased. the device contains 1024 blocks, composed by 64 pages cons isting in two nand structures of 32 series connected flash cells. a program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in typical 2ms on a 128k-byte(x8 device) block. data in the page mode can be read out at 50ns cycle time per word. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. commands, data and addresses are synchronously in troduced using ce#, we#, ale and cle input pin. the on-chip program/erase controller automates all progra m and erase functions including pulse repetition, where required, and internal verifica tion and margining of data. the modifying can be locked using the wp# input pin or using the extended lock block feature described later. the output pin rb# (open drain buffer) signals the status of the device during each operat ion. in a system with mul- tiple memories the rb# pins can be connected al l together to provide a global status signal. even the write-intensive systems can take advantage of th e hy27(u/s)f(08/16)1g2m extend ed reliability of 100k pro- gram/erase cycles by providing ecc (error correc ting code) with real time mapping-out algorithm. optionally the chip could be offered with the ce# don?t care function. this option allows the direct download of the code from the nand flash memory device by a microcontrol ler, since the ce# transitions do not stop the read opera- tion. the copy back function allows the opti mization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section withou t the time consuming serial data insertion phase. the cache program feature allows the data insertion in the ca che register while the data register is copied into the flash array. this pipelined program operation improves the program throughput when long files are written inside the memory. a cache read feature is also implemente d. this feature allows to dramatically improve the read throughput when con- secutive pages have to be streamed out. this device includes also extra features like otp/unique id area, automatic read at power up, read id2 extension. the hynix hy27(u/s)f(08/16)1g2m seri es is available in 48 - tsop1 12 x 20 mm , 48 - wsop1 12 x 17 mm, fbga 9.5 x 12 mm. 1.1 product list part number orization vcc range package hy27sf081g2m x8 1.70 - 1.95 volt 63fbga / 48tsop1 / 48wsop1 HY27SF161G2M x16 hy27uf081g2m x8 2.7v - 3.6 volt hy27uf161g2m x16
rev 0.6 / mar. 2005 5 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash figure1: logic diagram 9&& 966 35( :3 &/( $/( 5( :( &( ,2a,2 ,2a,2[2qo\ 5% io15 - io8 data input / outputs (x16 only) io7 - io0 data input / outputs cle command latch enable ale address latch enable ce# chip enable re# read enable we# write enable wp# write protect rb# ready / busy vcc power supply vss ground nc no connection pre power-on read enable table 1: signal names
rev 0.6 / mar. 2005 6 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 9vv ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 35( 9ff 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9vv 1$1')odvk 7623 [ 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [ 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk :623 [ 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 9vv ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 35( 9ff 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9vv 1$1')odvk :623 [ figure 2. 48tsop1 contac tions, x8 and x16 device figure 3. 48wsop1 contactions, x8 and x16 device
rev 0.6 / mar. 2005 7 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 1& 1& 1& 1& 1& 1& 1& 1& &/( $/( 9vv 9vv 9vv 9ff 9ff 1& 1& 1& :3 5( &( :( 5% 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 1& 1& 1& 1& 1& 1& 35( 1& 1& 1& 1& 1& 1& 1& $ % & ' ( ) * + - . / 0 1& 1& 1& 1& 1& 1& 1& 1& &/( $/( 9vv 9vv 9vv 9ff 9ff 1& 1& 1& :3 5( &( :( 5% 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 1& 1& 1& 1& 35( ,2 1& 1& 1& 1& 1& $ % & ' ( ) * + - . / 0 figure 4. 63fbga contactions, x8 device (top view through package) figure 5. 63fbga contactions, x16 device (top view through package)
rev 0.6 / mar. 2005 8 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 1 .2 pin description pin name description io0-io7 io8-io15(1) data inputs/outputs the io pins allow to input command, address and da ta and to output data during read / program operations. the inputs are latched on the rising edge of write enable (we#). the i/o buffer float to high-z when the device is desele cted or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the command register on the rising edge of write enable (we#). ale address latch enable this input activates the latching of the io inputs inside the command register on the rising edge of write enable (we#). ce# chip enable this input controls the selection of the device. when the device is busy ce# low does not deselect the memory. we# write enable this input acts as clock to latch command, addre ss and data. the io inputs are latched on the rise edge of we#. re# read enable the re# input is the serial data-out control, and wh en active drives the data onto the i/o bus. data is valid trea after the falling edge of re# which al so increments the internal column address counter by one. wp# write protect the wp# pin, when low, provides an hardware protection against undesired modify (program / erase) operations. rb# ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all the operations (read, write, er ase). an internal lock circuit prevent the insertion of command s when vcc is less than vlko vccq supply voltage for i/o buffers this pin is today internally connected to vcc an d must be shorted with vcc pin at system level vss ground nc not connected pre to enable power on auto read. when pre is a logic high, power on auto read mode is enabled, and when pre is a logic low, power auto read mode is disabled. power on auto read mode is available only on 3.3v device(hyuf(08/16)1g2m. not using power-on auto-read, co nnect it vss or leave it n.c. table 2: pin description note: 1. for x16 version only 2. a 0.1uf capacitor should be connect ed between the vcc supply voltage pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations.
rev 0.6 / mar. 2005 9 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a8a9a10a110000 3rd cycle a12 a13 a14 a15 a16 a17 a18 a19 4th cycle a20 a21 a22 a23 a24 a25 a26 a27 table 3: address cycle map(x8) io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a8a9a1000000 3rd cycle a11 a12 a13 a14 a15 a16 a17 a18 4th cycle a19 a20 a21 a22 a23 a24 a25 a26 table 4: address cycle map(x16) function 1st cycle 2nd cycle 3rd cycle acceptable command during busy read 1 00h 30h - read for copy-back 00h 35h - read id 90h - - reset ffh - - yes page program (start) 80h 10h - copy back pgm (start) 85h 10h - cache program 80h 15h - block erase 60h d0h - read status register 70h - - yes random data input 85h - - random data output 05h e0h - cache read start 00h 31h - cache read exit 34h - - extended read status 72h/73h/74h/75h - - yes table 5: command set
rev 0.6 / mar. 2005 10 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash cle ale ce# we# re# wp# mode h l l rising h x read mode command input l h l rising h x address input(4 cycles) h l l rising h h write mode command input l h l rising h h address input(4 cycles) lllrisinghhdata input ll l (1) h falling x sequential read and data output l l l h h x during read (busy) xxxxxhduring program (busy) xxxxxhduring erase (busy) xxxxxlwrite protect xxhxx0v/vccstand by table 6: mode selection note: 1. with the ce# don?t care option ce# high during latency time does not stop the read operation
rev 0.6 / mar. 2005 11 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 2. bus operation there are six standard bus operations that control the devi ce. these are command input, address input, data input, data output, write protect, and standby. typically glitches less than 5 ns on chip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 2.1 command input. command input bus operation is used to give a command to the memory device. command are accepted with chip enable low, command latch enable high, address latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modifying operation (write/erase) the write protect pin must be high. see figure 7 and table 14 for details of the timings requirements. command codes are always applied on io7:0, disregarding the bus configuration (x8/x16). 2.2 address input. address input bus operation allows the insertion of the memo ry address. to insert the 27 addresses needed to access the 1gbit 4 clock cycles are needed. addresses are accepted with chip enable low, a ddress latch enable high, com- mand latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify operation (write/erase) the write protec t pin must be high. see figure 8 and table 14 for details of the timings requirements. addresses are always applied on io7:0, disregarding the bus configuration (x8/x16). 2.3 data input. data input bus operation allows to feed to the device the data to be programm ed. the data insertion is serially and timed by the write enable cycles. data are accepted only wi th chip enable low, addre ss latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 9 and table 14 for details of the timings requirements. 2.4 data output. data output bus operation allows to read data from the me mory array and to check the st atus register content, the lock status and the id data. data can be serially shifted ou t toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latc h enable low. see figures 10,12,13 and table 14 for details of the timings requirements. 2.5 write protect. hardware write protection is activated when the write protec t pin is low. in this condition modify operation do not start and the content of the memory is not altered. write pr otect pin is not latched by wr ite enable to ensure the pro- tection even during the power up. 2.6 standby. in standby mode the device is deselected, output s are disabled and power consumption is reduced.
rev 0.6 / mar. 2005 12 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 3. device operation 3.1 page read. upon initial device power up, the device defaults to read mode. this operation is also initiated by writing 00h and 30h to the command register along with four address cycles. in two consecutive read operations, the second one doesn?t? need 00h command, which four address cy cles and 30h command initiates that operation. two types of operations are available : random read, serial page read. the random read mode is enabled when the page address is changed. the 2112 bytes (x8 device) or 1056 words (x16 device) of data within the selected page are transferred to the data regis- ters in less than 25us(tr). the system co ntroller may detect the completion of th is data transfer (tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 50ns cycle time by sequentially pulsing re#. the repetitive high to low tr ansitions of the re# clock make the device output the data starting from the selected column a ddress up to the last column address. the device may output random data in a page instead of th e consecutive sequential data by writing random data out- put command. the column address of next data, which is going to be out, may be changed to the address which follows random data output command. random data output can be operated multiple times re gardless of how many times it is done in a page. 3.2 page program. the device is programmed basically by page, but it does allo w multiple partial page programming of a word or consec- utive bytes up to 2112 (x8 device) or words up to 1056 (x16 device), in a single page program cycle. the number of consecutive partial page programming op eration within the same page without an intervening erase operation must not exceed 4 times for main array (x8 device:1time/512byte, x16 device:1time/256word) and 4 times for spare array (x8 device:1time/16byte ,x16 device:1time/8word). the addressing should be done in sequential order in a block 1 . a page program cycle consists of a serial data loading period in which up to 2112bytes (x8 device) or 1056wo rds (x16 device) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input comma nd (80h), followed by the four cycle address inputs and then serial data. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address of next data, which will be entered, may be changed to the address which follows random data input co mmand (85h). random data input may be operated multi- ple times regardless of how many times it is done in a page. the page program confirm command (10h) initiates the prog ramming process. writing 10h alone without previously entering the serial data will not initia te the programming process. the internal write state controller automatically exe- cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status regi ster command may be entered to read the status register. the system controller can detect the completion of a progra m cycle by monitoring the rb# output, or the status bit (i/ o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit (i/o 0) may be checked. the internal write verify detects only errors for "1"s that are not successfully prog rammed to "0"s. the command register remains in read sta- tus command mode until another valid co mmand is written to the command register. figure 15 details the sequence.
rev 0.6 / mar. 2005 13 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 3.3 block erase. the erase operation is done on a block basis. block address lo ading is accomplished in two cycles initiated by an erase setup command (60h). only address a18 to a27 (x8) or a17 to a26 (x16) is valid while a12 to a17 (x8) or a11 to a16 (x16) is ignored. the erase confirm command (d0h) followin g the block address loading in itiates the internal erasing process. this two-step sequence of setup followed by ex ecution command ensures that memory contents are not acci- dentally erased due to ex ternal noise conditions. at the rising edge of we# after the erase confirm command input, the internal write controller handles erase and erase-verify. once the erase process starts, the read status register co mmand may be entered to read the status register. the sys- tem controller can detect the completion of an erase by monitoring the rb# outp ut, or the status bit (i/o 6) of the status register. only the read status command and reset command are valid while erasing is in progress. when the erase operation is completed, the write status bit (i/o 0) may be checked. figure 19 details the sequence. 3.4 copy-back program. the copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. since the time -consuming cycles of serial access and re-l oading cycles are removed, the system per- formance is improved. the benefit is espe cially obvious when a portion of a bloc k is updated and the rest of the block also need to be copied to the newl y assigned free block. the operation for performing a copy-back program is a sequential execution of page-read withou t serial access and copying-program wi th the address of destination page. a read operation with "35h" command and the address of the source page moves the whole 2112byte (x8 device) or 1056word (x16 device) data into the internal data buffer. as soon as the device returns to ready state, copy back command (85h) with the address cycles of destination page may be written. the program confirm command (10h) is required to actually begin the programmi ng operation. data input cycle for modi fying a portion or multiple distant por- tions of the source page is allowed as shown in figure 17. "when there is a program-failure at copy-back operatio n, error is reported by pass/fail status. but, if copy-back operations are accumulated over time, bit e rror due to charge loss is not checked by external error detection/correction scheme. for this reason, two bit error correction is recommended for the use of copy-back operation." figure 17 shows the command sequ ence for the copy-back operation. 3.5 read status register. the device contains a status register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or eras e operation is completed successfully. after writing 70h command to the com- mand register, a read cycle outputs the co ntent of the status register to the i/ o pins on the falling edge of ce# or re#, whichever occurs last. this two line control allows the system to poll th e progress of each device in multiple memory connections even when rb# pins are common-wired. re# or ce# does not need to be toggled for updated status. refer to table 15 for specific status register defi nitions. the command register remains in status read mode until further commands are issued to it. th erefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. see figure 11 for details of the read status operation.
rev 0.6 / mar. 2005 14 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 3.6 read id. the device contains a product identification mode, initiate d by writing 90h to the command register, followed by an address input of 00h. four read cycles sequentially output the manufacturer code (adh), and the device code and 00h, 4th cycle id, respectively. the command register remains in read id mode until further commands are issued to it. figure 20 shows the operatio n sequence, while tables 16, 17 explain the byte meaning. 3.7 reset. the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operat ion will abort these operatio ns. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value e0h when wp# is high. if the device is already in reset state a new reset command will not be accepted by the command regi ster. the rb# pin transitions to low for trst after the reset command is written. refer to figure 30. 3.8 cache program. cache program is an extension of page program, which is executed with 2112byte (x8 device) or 1056word (x16 device) data registers, and is available only within a block. since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. after writing the first set of data up to 2112byte (x8 device) or 1056word (x16 device ) into the selected cache registers, cache program com- mand (15h) instead of actual page program (10h) is input to make cache registers free an d to start internal program operation. to transfer data from cache registers to data registers, the device remains in busy state for a short period of time (tcbsy) and has its cache registers ready for the ne xt data-input while the internal programming gets started with the data loaded into data register s. read status command (70h) may be i ssued to find out when cache registers become ready by polling the cache-busy st atus bit (i/o 6). pass/fail status of only the previous page is available upon the return to ready state. when the ne xt set of data is input with the cache program command, tcbsy is affected by the progress of pending internal programming. the programmi ng of the cache registers is initiated only when the pending program cycle is finished and the data registers are av ailable for the transfer of data from cache registers. the status bit (i/o5) for internal ready/busy may be polled to identify the completion of internal programming. if the system monitors the progress of programming only wi th rb#, the last page of th e target programming sequence must be programmed with actual page program command (10h). if the cache program command (15h) is used instead, status bit (i/o5) must be polled to find out when the last programming is actually finished before starting other operations such as read. pass/fail status is available in two steps. i/o 1 returns with the status of the previous page upon ready or i/o6 status bit chan ging to "1", and later i/o 0 with the st atus of current page upon true ready (returning from internal programming) or i/o 5 status bit ch anging to "1". i/o 1 may be read together when i/o 0 is checked. see figure 18 for more details. note : since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completi on of the previous cycle, which can be expressed as the following formula. tprog= program time for the last page+ program time for the ( last -1 )th page - (program command cycle time + last page data loading time) 3.9 cache read
rev 0.6 / mar. 2005 15 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash cache read operation allows automatic download of consecut ive pages, up to the whole device. immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. start address of 1st page is at page start (a<10:0>=00h), af ter 1st latency time (tr) , automatic data download will be uninterrupted. in fact latency time is 25us, while downlo ad of a page require at least 100us for x8 device (50us for x16 device). cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache read) user can check operation status using : - rb# ( ?0? means latency ongoing, down load not possible, ?1? mean s download of n page po ssible, even if device internally is active on n+1 page - status register (sr<6> behave like rb#, sr<5> is ?0? when device is internally reading and ?1? when device is idle) to exit cache read operation a cache read exit command ( 34h) must be issued. this command can be given any time (both device idle and reading). if device is active (sr<5>=0) it will go idle within 5us, whil e if it is not active, device itself will go busy for a time shorter then tcbsy before becoming again idle and ready to accept any further commands. if user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command. random data output is not available in cache read. cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
rev 0.6 / mar. 2005 16 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 4. other features 4.1 data protection. the device is designed to offer protection from any involu ntary program/erase during powe r-transitions. an internal voltage detector disables all functions whenever vcc is belo w about 1.5v. wp# pin provides hardware protection and is recommended to be kept at vil during power-up and power-down. a recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in figure 26. the two-step command sequence for program/erase provides additional software protection. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the co mpletion of a page program, erase, copy-back, cache program and random read completion. th e rb# pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operatio n). it returns to high when th e internal controller has fin- ished the operation. the pin is an open-d rain driver thereby allowing two or mo re rb# outputs to be or-tied. because pull-up resistor value is related to tr(r b#) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart (fig.27). its va lue can be determined by the following guidance. 4.3 power-on auto-read the device is designed to offer automa tic reading of the first page without command and address input sequence dur- ing power-on. an internal voltage detector enables auto-page read functi ons when vcc reaches about 1.8v. pre pin controls activa- tion of auto- page read function. auto-page read function is enabled only when pre pin is logic high state. serial access may be done after power-on without latency. power- on auto read mode is available only on 3.3v device (hy27uf(08/16)1g2m).
rev 0.6 / mar. 2005 17 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 4.4 multiple die (2gbit / 4gbit) concurre nt operations and extended read status when the 1gbit is stacked to form a 2gbit ddp or a 4gbi t qdp some concurrent operations (like erase while read, read while write, etc.) are available. moreover an extended read status register feature is included to check the sta- tus of each stacked device. in more detail s it is possible to run a first operation selecting the first 1gbit, then activate a concurrent operation on the second (or third or fourth) device, checking the progression of these operations by the use of the extended read status register feature. the command sequence to be used is shown in table 7. the result is the typical read status pattern. table 7: extended read status register commands function command read status 1st device (ax<= 0x07ffffff) 72h read status 2nd device (0x07ffffff rev 0.6 / mar. 2005 18 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash symbol parameter value unit 1.8v 3.3v t a ambient operating temperature (commercial temperature range) 0 to 70 0 to 70 ambient operating temperature (extended temperature range) -25 to 85 -25 to 85 ambient operating temperature (industrial temperature range) -40 to 85 -40 to 85 t bias temperature under bias -50 to 125 -50 to 125 t stg storage temperature -65 to 150 -65 to 150 v io (2) input or output voltage -0.6 to 2.7 -0.6 to 4.6 v vcc supply voltage -0.6 to 2.7 -0.6 to 4.6 v table 9: absolute maximum ratings note: 1. except for the rating ?operating temperature rang e?, stresses above those listed in the table ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. 2. minimum voltage may undershoot to -2v during tran sition and for less than 20ns during transitions.
rev 0.6 / mar. 2005 19 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash $''5(66 5(*,67(5 &2817(5 352*5$0 (5$6( &21752//(5 +9*(1(5$7,21 &200$1' ,17(5)$&( /2*,& &200$1' 5(*,67(5 '$7$ 5(*,67(5 ,2 5( %8))(56 <'(&2'(5 3$*(%8))(5 ; ' ( & 2 ' ( 5 0elw0elw 1$1')odvk 0(025<$55$< :3 &( :( &/( $/( 35( $a$ figure 6: block diagram
rev 0.6 / mar. 2005 20 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash parameter symbol test conditions 1.8volt 3.3volt unit min typ max min typ max operating current sequential read i cc1 t rc =50ns, ce#=v il , i out =0ma -815-1020ma program i cc2 --815-1020ma erase i cc3 --815-1020ma stand-by current (ttl) i cc4 ce#=v ih , pre=wp#=0v/vcc --1- 1ma stand-by current (cmos) i cc5 ce#=vcc-0.2, pre=wp#=0v/vcc -1050-1050ua input leakage current i li v in =0 to 3.6v - - 10 -- 10 ua output leakage current i lo v out =0 to 3.6v - - 10 -- 10 ua input high voltage v ih -vcc-0.4- vcc+ 0.3 2- vcc+ 0.3 v input low voltage v il - -0.3 - 0.4 -0.3 - 0.8 v output high voltage level v oh i oh =-100ua vcc-0.1 - - - - - v i oh =-400ua - - - 2.4 - - v output low voltage level v ol i ol =100ua - - 0.1 - - - v i ol =2.1ma - - - - - 0.4 v output low current (rb#) i ol (rb#) v ol =0.1v 3 - 4 - - - ma v ol =0.4v - - - 8 - 10 ma table 10: dc and operating characteristics parameter value 1.8volt 3.3volt input pulse levels 0v to vcc 0.4v to 2.4v input rise and fall times 5ns 5ns input and output timing levels vcc / 2 1.5v output load (1.7v - 1.95volt & 2.7v - 3.6v) 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf output load (3.0v - 3.6v) - 1 ttl gate and cl=100pf table 11: ac conditions
rev 0.6 / mar. 2005 21 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash item symbol test condition min max unit input / output capacitance (1) c i/o v il =0v - 10 pf input capacitance(1) c in v in =0v - 10 pf table 12: pin capacita nce (ta=25c, f=1.0mhz) note: 1. for the stacked devices version the input capaci tance is and the i/ o capacitance is parameter symbol min typ max unit program time t prog - 300 700 us dummy busy time for cache program t cbsy -3700us dummy busy time for the lock or lock-tight block t lbsy -510us number of partial program cycles in the same page main array nop - - 4 cycles spare array nop - - 4 cycles block erase time t bers -23ms table 13: program / erase characteristics
rev 0.6 / mar. 2005 22 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash parameter symbol 1.8volt 3.3volt unit min max min max cle setup time t cls (4) 00ns cle hold time t clh (4) 10 10 ns ce# setup time t cs 00ns ce# hold time t ch 10 10 ns we# pulse width t wp (4) 25 (1) 25 (1) ns ale setup time t als (4) 00ns ale hold time t alh (4) 10 10 ns data setup time t ds (4) 20 20 ns data hold time t dh 15 15 ns write cycle time t wc (4) 50 50 ns we# high hold time t wh 20 20 ns ale to data loading time tadl 100 100 ns data transfer from cell to register t r 25 25 us ale to re# delay (id read) tar 10 10 ns cle to re# delay tclr 10 10 ns ready to re# low t rr 20 20 ns re# pulse width t rp (4) 25 25 ns we# high to busy t wb 100 100 ns read cycle time t rc (4) 50 50 ns re# access time t rea (4) 30 30 ns re# high to output high z t rhz 30 30 ns ce# high to output high z t chz 20 20 ns re# high hold time t reh (4) 20 20 ns output high z to re# low t ir 00ns ce# access time t cea 45 45 ns we# high to re# low t whr 60 60 ns device resetting time (read / program / erase) t rst 5/10/500 (3) 5/10/500 (3) us table 14: ac timing characteristics note: 1. if t cs is less than 10ns t wp must be minimum 40ns, otherwise, t wp may be minimum 35ns. 2. the time to ready depends on the value of the pull-up resistor tied to rb# pin 3. if reset command (ffh) is written at ready st ate, the device goes in to busy for maximum 5us 4. these parameters are applied to the errata. 5. tadl is the time from the we# rising edge of final address cycle to the we# rising edge of first data cycle.
rev 0.6 / mar. 2005 23 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash io pagae program block erase cache program read cache read coding 0 pass / fail pass / fail pass / fail (n) na pass: ?0? fail: ?1? 1 na na pass / fail (n-1) na pass: ?0? fail: ?1? (only for cache program, else don?t care) 2na na na na - 3na na na na - 4na na na na - 5 ready/busy ready/busy p/e/r controller bit ready/busy p/e/r controller bit active: ?0? idle: ?1? 6 ready/busy ready/busy cache register free ready/busy ready/busy busy: ?0? ready?: ?1? 7 write protect write protect write protect write protect protected: ?0? not protected: ?1? table 15: status register coding device identifier byte description 1st manufacturer code 2nd device identifier 3rd don't care 4th page size, block size, spare size, organization table 16: device identifier coding
rev 0.6 / mar. 2005 24 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash description io7 io6 io5-4 io3 io2 io1-0 page size (without spare area) 1k 2k reserved reserved 0 0 0 1 1 0 1 1 spare area size (byte / 512byte) 8 16 0 1 serial access time standard (50ns) fast (30ns) 0 1 block size (without spare area) 64k 128k 256k reserved 0 0 0 1 1 0 1 1 organization x8 x16 0 1 not used reserved table 17: 4th byte of devi ce identifier description w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2a w'+ w'6 w$/6 w$/+ w&/+ w&+ figure 7: command latch cycle
rev 0.6 / mar. 2005 25 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash w:& w:& w:& w&6 w:3 w$/+ w$/6 w$/+ w$/+ w$/+ w$/+ w$/+ w$/+ w'6 w'6 w:+ w:+ w:+ w'6 w'6 w'+ w'+ w'+ w'+ w:3 w:3 w:3 w&/6 &ro$gg &ro$gg 5rz$gg 5rz$gg &/( $/( &( ,2[ :( figure 8: address latch cycle
rev 0.6 / mar. 2005 26 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash w:& w$/6 w&/+ w&+ w:3 w:+ ',1 ',1 ',1ilqdo w:+ w'+ w'+ w'+ w'6 w'6 w'6 w:3 w:3 &/( $/( &( ,2[ :( figure 10: sequential out cycle after read (cle=l, we#=h, ale=l) w &($ w 5($ w 53 w 5($ w 5+= w 5+= 'rxw 'rxw 'rxw w &+= w 2+ w 2+ w 5($ w 5(+ w 5& w 55 &( 5( 5% ,2[ figure 9. in put data latch cycle
rev 0.6 / mar. 2005 27 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash figure 11: status read cycle w &/6 w &/5 w &/+ w &6 w &+ w :3 w :+5 w &($ w '6 w 5($ w &+= w 5+= k 6wdwxv2xwsxw w '+ w ,5 &( :( ,2 [ &/( 5( &/( $/( &( ,2[ :( 5( 5' w :& w &/5 w 55 k k &ro$gg &roxpq$gguhvv 5rz$gguhvv &ro$gg 5rz$gg 5rz$gg %xv\ 'rxw1 'rxw1 'rxw0 w :% w $5 w 5 w 5& w 5+= w 2+ figure 12: read1 operation (read one page)
rev 0.6 / mar. 2005 28 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash &/( $/( &( ,2[ :( 5( 5' w :& w &/5 w 55 k k &ro$gg &roxpq$gguhvv 5rz$gguhvv &ro$gg 5rz$gg 5rz$gg %xv\ 'rxw1 'rxw1 'rxw0 w :% w $5 w 5 w 5& w 5+= w 2+ figure 13: read1 operation intercepted by ce#
rev 0.6 / mar. 2005 29 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash &/( $/( &( 5( 5% ,2[ :( w&/5 k &roxpq$gguhvv 5rz$gguhvv %xv\ k k (k 'rxw1 'rxw0 'rxw1 'rxw0 &ro$gg 5rz$gg 5rz$gg &ro$gg &roxpq$gguhvv &ro$gg &ro$gg w5 w5& w:% w$5 w55 w:+5 w5($ figure 14 : random data output
rev 0.6 / mar. 2005 30 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash figure 15: page program operation &/( $/( &( 5( 5% ,2[ :( w:& k &ro$gg 6huldo'dwd ,qsxw&rppdqg &roxpq$gguhvv 5rz$gguhvv 5hdg6wdwxv &rppdqg 3urjudp &rppdqg ,2r 6xffhvvixo3urjudp ,2r (uurulq3urjudp ;ghylfhp e\wh ;ghylfhp zrug xswrp%\wh 6huldo,qsxw &ro$gg 5rz$gg 5rz$gg 'lq 1 'lq 0 k k ,2r w:& w$'/ w:& w:% w352*
rev 0.6 / mar. 2005 31 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash &/( $/( &( 5( 5% ,2[ :( w:& k 'lq 1 'lq 0 'lq - 'lq . k k k ,2 &ro$gg &ro$gg &ro$gg &ro$gg 5zr$gg 5zr$gg w:& w$'/ w$'/ w:& w:% w352* 6huldo'dwd ,qsxw&rppdqg 5dqgrp'dwd ,qsxw&rppdqg &roxpq$gguhvv &roxpq$gguhvv 5rz$gguhvv 6huldo,qsxw 6huldo,qsxw 3urjudp &rppdqg 5hdg6wdwxv &rppdqg figure 16 : random data in
rev 0.6 / mar. 2005 32 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash &/( $/( &( 5( 5% ,2[ :( w:& w:% w:% w352* w$'/ w5 k &roxpq$gguhvv5rz$gguhvv &roxpq$gguhvv %xv\ %xv\ &rs\%dfn'dwd ,qsxw&rppdqg ,2 6xffhvvixo3urjudp ,2 (uurulq3urjudp 5rz$gguhvv k k k k ,2 'dwd 'dwd1 &ro$gg 5rz$gg 5rz$gg &ro$gg &ro$gg 5rz$gg 5rz$gg &ro$gg 5hdg6wdwxv &rppdqg figure 17 : copy back program
rev 0.6 / mar. 2005 33 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash &/( $/( &( 5( 5% ,2[ :( 5% ,2[ ([&dfkh3urjudp w:& k k ,2 3urjudp&rqilup &rppdqg7uxh /dvw3djh,qsxw 3urjudp 0d[wlphvuhshdwdeoh w&%6<pd[xv w&%6< &ro$gg 5rz$gg'dwd w&%6< w&%6< w352* 6huldo'dwd ,qsxw&rppdqg &roxpq$gguhvv 5rz$gguhvv 6huldo,qsxw 3urjudp &rppdqg 'xpp\ k k $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw k k k k k k k k k 'lq 1 'lq 0 'lq 1 'lq 0 &ro$gg k &ro$gg 5rz$gg 5rz$gg &ro$gg &ro$gg 5rz$gg 5rz$gg w:% w352* w:% w&%6< figure 18 : cache program
rev 0.6 / mar. 2005 34 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash w:& &/( &( :( $/( 5( ,2 a 5% w:% w%(56 %86< k ,2 'k k $xwr%orfn(udvh6hwxs &rppdqg (udvh&rppdqg 5hdg6wdwxv &rppdqg ,2 6xffhvvixo(udvh ,2 (uurulq(udvh 5rz$gguhvv vw$gg qg$gg figure 19: block erase op eration (erase one block) k &/( &( :( $/( 5( ,2[ k w5($ 5hdg,'&rppdqg $gguhvvf\foh 0dnhu&rgh 'hylfh&rgh $'k )k k [[k 'rq?wfduh wkf\foh figure 20: read id operation
rev 0.6 / mar. 2005 35 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash k ' 5hdgvwsdjh 5hdgqgsdjh 5hdgugsdjh 5hdgwksdjh ,goh ,goh ' ' ' ' ' ' ' ' ' ' ' ' $gg $gg $gg $gg k ?v ?v ?v ?v ?v ?v ?v &/( $/( :( 5( ,qwhuqdorshudwlrq 6wdwxv5hjlvwhu 65! figure 21: start address at page start :a fter 1st latency uninterrupted data flow ' ,goh ,goh ?v ?v ?v ,qwhuuxswhg 5hdgqsdjh 5hdgqsdjh ' ' k ' ' ' ' &/( $/( :( 5( ,qwhuqdo rshudwlrq 8vhufdq khuhilqlvk uhdglqj1 sdjh 1sdjh fdqqrweh uhdg figure 22: exit from cache read in 5m s when device internally is reading
rev 0.6 / mar. 2005 36 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash &( :( $/( &/( 5( &(grq?wfduh ,2[ 5% k $ ? $ ?? $ ??? $ ???? ' ' ' figure 23: page read with ce# don?t care option
rev 0.6 / mar. 2005 37 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 9row 9 7+ 9 && w $xwrpdwlf5hdgdw3rzhu2q figure 24: automatic read at power on ))k w 567 :( $/( &/( 5( ,2[ 5% figure 25: reset operation
rev 0.6 / mar. 2005 38 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash :3 :( 9ff w 9 7+ figure 26: power on and data protection timing vth = 1.5 volt for 1.8 volt supply device s; 2.5 volt for 3.3 volt supply devices * see the application note.1
rev 0.6 / mar. 2005 39 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 5sydoxhjxlghqfh 5splq zkhuh,/lvwkhvxpriwkhlqsxwfxuuqwvridooghylfhvwlhgwr wkh5%slq 5spd[lvghwhuplqhge\pd[lpxpshuplvvleoholplwriwu #9ff 97d ?&& / s) )lj5syvwuwi 5syvlexv\ 9ff0d[9 2/ 0d[ 9 p$?, / , 2/ ?, / 5s lexv\ 5srkp lexv\ lexv\>$@ wuwi>v@ wi %xv\ 5hdg\ 9ff 9 wu wi 9 9ff q p n n n n q p q p *1' 'hylfh rshqgudlqrxwsxw 5% figure 27: ready/busy pin electrical specifications
rev 0.6 / mar. 2005 40 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash figure 28: page programming within a block m???g???gszig????g??gtzig???? kh{hgpugagk???goxp k???go][p k???g???????? w???g]z w???gzx w???gy w???gx w???gw o][p a ozyp a ozp oyp oxp l?upgy?????g????g???????gow??????????p kh{hgpugagk???goxp k???go][p k???g???????? w???g]z w???gzx w???gy w???gx w???gw o][p a oxp a ozp ozyp oxp
rev 0.6 / mar. 2005 41 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash bad block management devices with bad blocks have the same quality level and th e same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transi stor. the devices are supplied with al l the locations inside valid blocks erased(ffh). the bad block information is wr itten prior to shipping . any block where the 1st byte in the spare area of the 1st or 2nd page(if the 1st page is bad) does not contain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recog- nize the bad blocks based on the original information it is recommended to crea te a bad block table following the flow- chart shown in figure 29. block replacement over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. as the failure of a page program operatio n does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the re st of the replaced block to an available valid block. the copy back program command can be used to copy the data to a valid block. see the ?copy back program? section for more details. refer to table 18 for the recommended procedure to follow if an error occurs during an operation. operation recommended procedure erase block replacement program block replacement or ecc read ecc table 18: block failure <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh figure 29: bad block management flowchart
rev 0.6 / mar. 2005 42 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 5. appendix : extra features 5.1 automatic page0 read after power up the timing diagram related to this operation is shown in fig. 24 due to this functionality the cpu can dire ctly download the boot loader from the first page of the nand flash, storing it inside the internal cache and starting the execution after the download completed. 5.2 stacked devices access a small logic inside the devices allows th e possibility to stack up to 4 devices in a single package without changing the pinout of the memory. to do this the internal address regi ster can store up to 29 addresses (512 mbyte addressing field) and basing on the 2 msb pattern ea ch device inside the packag e can decide if remain active (1 over 4) or ?hang- up? the connection entering the stand-by. 5.3 addressing for program operation within a block, the pages must be programmed consecutively from lsb (least significant bi t) page of the block to msb (most significant bit) page of the block. random address programming is prohibited. see fig. 28.
rev 0.6 / mar. 2005 43 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash table 19: 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters min typ max a 1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.050 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e 0.500 l 0.500 0.680 alpha 0 5 figure 30. 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline ' $ ',( $ h % / . ( ( & &3 $
rev 0.6 / mar. 2005 44 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash symbol millimeters min typ max a 0.700 a1 0 0.080 a2 0.540 0.620 b 0.130 0.230 c 0.065 0.175 cp 0.050 d 11.910 12.000 12.120 e 16.900 17.000 17.100 e1 15.300 15.400 15.500 e 0.500 l 0.450 0.750 alpha 0 8 figure 31. 48-wsop1 - 48-lead plas tic very very thin small outline, 12 x 17mm, package outline table 20: 48-wsop1- 48-lead pla stic thin small outline, 12 x 17mm, package mechanical data $ $ $ ( ( & h % $qjoh doskd ' ( . &3
rev 0.6 / mar. 2005 45 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash symbol millimeters min typ max a 0.80 0.90 1.00 a1 0.25 0.30 0.35 a2 0.55 0.60 0.65 b 0.40 0.45 0.50 d 9.40 9.50 9.60 d1 4.00 d2 7.20 e 11.90 12.00 12.10 e1 5.60 e2 8.80 e0.80 fd 2.75 fd1 1.15 fe 3.20 fe1 1.60 sd 0.40 se 0.40 ' ' 6' )' )' $ $ $ 6( )( )( ( ( %$//3$ ( h h ggg h e ' figure 32. fbga 63 - 9.5 x 12, 6 x 8 ba ll array 0.8mm pitch, pakage outline note : drawing is not to scale. table 21: fbga63 - 9.5 x 12, 6 x 8 ball ar ray 0.8mm pitch, pakage mechanical data
rev 0.6 / mar. 2005 46 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash application note 1. power-on/off sequence after power is on, the device starts an internal circuit initialization when the po wer supply voltage reaches a specific level. the device shows its internal initia lization status with the read y/busy signal if initializa tion is on progress. while the device is initializing, the device se ts internal registeries to default value and generates internal biases to operate circuits. typically the initializi ng time of 20us is required. power-off or power failure before write/erase operation is complete will cause a loss of data. the wp# signal helps user to protect not only the data integrity but also device circuitry from being damaged at power-on/off by keeping wp# at vil during power-on/off. for the device to operate stably, it is highly re commended to operate the device as shown fig.33. :3 9 ,/ 9 ,+ 9'hylfh9 9'hylfh9 9'hylfh9 :( 9 ,/ xv 5hdg\ %xv\ ,qlwldol]hdwsrzhurq 9 9&& 2wkhuv 3lqv ,/ figure 33: power-on/off sequence
rev 0.6 / mar. 2005 47 preliminary hy27uf(08/16)1g2m series hy27sf(08/16)1g2m series 1gbit (128mx8bit / 64 mx16bit) nand flash 2. automatic sleep mode for low power consumption the device provides the automatic sleep function for low power consumption. the device enters the automatic sleep mode by keeping ce# at vih level for 10us without any additional command input, and exits simply by lowering ce# to vil level. typically, consecutive operation is executable righ t after deactivating the automatic sleep mode, while tcs of 2us is required prior to following operation as shown in fig.34. ,2[ k :( &( xv0lq&( 9 ,+ ,+ k xv0lq $xwr6ohhs ,2[ k $gguhvvlqsxw $gguhvvlqsxw 'dwdrxwsxw froxpq/a0 'dwdlqsxw froxpq/a0 5( &( xv0lq&( 9 'dwdrxwsxw froxpq0a1 'dwdlqsxw froxpq0a1 $xwr6ohhs k 3urjudp2shudwlrq 5hdg2shudwlrq xv0lq figure 34: tcs setting when deactivating the auto sleep mode

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